The present invention generally relates to a data processing system, and more particularly to a circuit for controlling memories in a microprocessor LSI and microprocessor peripheral circuits.
Dynamic memories are generally referred to as DRAM (Dynamic Random Access Memory). Specifications of typical dynamic memory LSI's are described in, for example, "Hitachi IC Memory Data Book 3 (DRAM, DRAM Modules)", pp. 445-464. A dynamic memory described in this document has ten address input terminals indicated by A0-A9 which are shared to receive row and column addresses (see page 448). Also according to this literature, a read/write access requires a row address and a column address to be provided to the dynamic memory LSI in this order (see page 454), wherein read access time is 70 nanoseconds after the establishment of the externally provided address (1 nanosecond=1.times.10.sup.-9 second). Alternative to this read/write access, if a fast page mode (page 461) is used, after the first row and column addresses have been transferred, as long as second and subsequent accesses are made to the same row, transfer of the row address can be omitted, with the result that read access time required for the second and subsequent read accesses is reduced to 20 nanoseconds from the establishment of the external address.
An example of a DRAM control function designed for a conventional microprocessor (hereinafter simply called the "processor") is described in "Hot Chips IV", pp. 4.2.2-4.2.12, August. 1992, held in Stanford University. On page 4.2.3 of this document, a drawing is illustrated in which a processor LSI is directly connected to two banks of DRAM chips. Also, timing charts on pages 4.2.7 and 4.2.8 of this document respectively include descriptions "Check fast page cache-hit" and "Check fast page cache-miss", from which it can be predicted that the fast page mode of the dynamic memory is used under certain hit conditions within the processor. This operation would be enabled, for example, by storing a row address with which a dynamic memory has been accessed at the previous time. The above-mentioned document, however, does not at all refer to how to use two-bank DRAM's or the relation between the cache-hit of the high speed mode and the two-bank DRAM's.
Assume now a conventional processor LSI which includes, among its terminals, dynamic memory address terminals which are used for both row and column addresses. FIG. 2 shows an example of accesses performed by this processor. It should be noted that in FIG. 2, the horizontal direction represents the time axis, and reference numeral 201 designates an access request from the processor; 202 dynamic address terminals A0-A9 of the processor; 203 a row address strobe (RAS-n) signal of a dynamic memory; and 204 a column address strobe (CAS-n) signal of the dynamic memory. A suffix "-n" to a signal line indicates that a signal on that line is of negative polarity.
This exemplary access occurs, for example, when a block of data, i.e., the contents of a memory in a certain region, is copied to another region of the memory. In FIG. 2, a region from address A000 is copied to a region from address 7040. It should be noted that in this specification memory addresses are indicated in hexadecimal number. An explanatory diagram 205 shows how to use 32 bits of a physical address. Specifically, bits (30-31) of the physical address are assigned to an in-word address; bits (21-29) to a column address of a dynamic memory; and bits (11-20) to a row address of the dynamic memory. Here, bit (i) indicates the position of the i-th bit from the leftmost bit which is designated as bit 0 position. The copy is carried out by the following time-sequential operations.
Operation 1: The contents at address A000 are read. A row address and column address are transferred to the dynamic memory. The row address given by the bit positions (11-20) of the physical address is "14", then the column address given by the bit positions (21-29) is zero.
Operation 2: The contents of address A004 are read. Since the row address at this time is the same as that at the previous time, transfer of the row address to the dynamic memory is omitted. Thus, the column address only is transferred to the dynamic memory.
Operation 3: The contents of address A000 are written into address 7040. A row address and column address for this location are transferred to the dynamic memory.
Operation 4: The contents of address A004 are written into address 7044. Since the row address at this time is the same as that at the previous time, the transfer of the row address to the dynamic memory is omitted. Thus, the column address only is transferred to the dynamic memory.
Since the subsequent four accesses perform similar operations to the above, explanation thereon will be omitted.
As shown by the example of FIG. 2, the prior art example has a problem that if a row address of a memory location (source), from which data is read and a row address of a memory location (destination) to which the data is written are different in the block copy processing, the fast mode for omitting the transfer of a row address of the dynamic memory is prohibited each time the access source and destination are switched.